Programmable logic devices (“PLDs”) (also sometimes referred to as CPLDs, PALs, PLAs, FPLAs, EPLDs, EEPLDs, LCAs, FPGAs, or by other names), are well-known integrated circuits that provide the advantages of fixed integrated circuits with the flexibility of custom integrated circuits. Such devices are well known in the art and typically provide an “off the shelf” device having at least a portion that can be electrically programmed to meet a user's specific needs. Application specific integrated circuits (“ASICs”) have traditionally been fixed integrated circuits, however, it is possible to provide an ASIC that has a portion or portions that are programmable; thus, it is possible for an integrated circuit device to have qualities of both an ASIC and a PLD. The term PLD as used herein will be considered broad enough to include such devices.
PLDs may include blocks of logic elements, sometimes referred to as logic array blocks (“LABs”; also referred to by other names, e.g., “configurable logic blocks,” or “CLBs”). Logic elements (“LEs”, also referred to by other names, e.g., “logic cells”) may include a look-up table (LUT) or product term, carry-out chain, register, and other elements. The LE is typically the smallest repeatable functional block of a PLD.
LUTs generally include configurable elements holding configuration data that determines the particular function or functions carried out by the logic element. A typical LUT circuit may include ram bits that hold data (a “1” or “0”). However, other types of configurable elements may be used. Some examples may include static, magnetic, ferro-electric or dynamic random access memory, electrically erasable read-only memory, flash, fuse, and anti-fuse programmable connections. For purposes herein, the generic term “memory element” will be used to refer to any programmable element that may be configured to determine functions implemented by a LUT. A typical LUT circuit used as a logic element provides an output signal that is a function of multiple input signals. The particular logic function that is provided may be determined by programming the LUT's memory elements.
The k-value of a LUT is the maximum number of inputs for a combinatorial logic function that the LUT will perform. For example a LUT of k=4, or 4-LUT, will perform combinatorial logic functions of up to 4 inputs. A k-LUT can also perform logic functions having fewer than k inputs. And, a “complete” k-LUT can perform all possible k input combinatorial logic functions as well as all possible j input functions where j is less than k.
The higher the k-value of a LUT, the greater the number of logic functions the LUT will perform. Additionally, typically, the higher the k-value of a LUT, the higher the performance of the LUT, where performance indicates the clock speed of a LUT averaged over different logic functions performed by the LUT. Thus, using a higher k-value LUT in PLD design may be desirable. However, generally, the higher the k-value of the LUT, the greater the silicon area that is taken up by the LUT, and therefore, the more expensive it is to implement.